The Xilinx SPI-4.2 core provides a script called gen_sim_model[.bat] in the "/test/vhdl and /test/verilog" subdirectories when generating the core through COREGen. When running this script, NGDBuild might produce any of the following warnings:
WARNING:NgdBuild:440 - FF primitive 'U0/clkdomain0/srts/output_ff' has
unconnected output pin
WARNING:NgdBuild:454 - logical net
'U0/core0/queue0/rrdadrx/FIFO_addr_gray_ffs<0>' has no load"
WARNING:NgdBuild:440 - FF primitive 'U0/sync0/ssses/output_ff' has unconnected
WARNING:NgdBuild:440 - FF primitive 'U0/core0/data0/u10/dip4_val/FF5' has
unconnected output pin"
These warnings are valid and expected due to the signals that are not used being used in the SPI4.2 core. These warnings have no impact on the functionality of the core and can be safely ignored.