AR# 20022

LogiCORE SPI-4.2 (POS-PHY L4) - How do I find the optimal IOBDELAY (ISERDES) value or the Phase Shift (DCM) value for my system? (also applies to SPI4-4.2 Lite Core)


When targeting a Virtex-4 or Virtex-5 device, Dynamic Phase Alignment is recommended rather than Static Alignment because there are performance advantages with Dynamic Phase Alignment. However, when using a SPI-4.2 Core in a Static Alignment mode, you can perform the Static Alignment in the following two ways:

- Select Static Alignment with Global Clocking

- Select Static Alignment with Regional Clocking

NOTE: Dynamic Phase Alignment is not available with the Lite Core.


Global Clocking (DCM)

If Global Clocking is selected as the clocking option, the phase shifting feature of the DCM is used to shift the RDClk with respect to incoming data (RDat). In this case, it is important to determine the optimal Phase Shift value for the DCM. See (Xilinx Answer 16112) on how to determine the optimal Phase Shift value for your SPI-4.2 DCM.

Regional Clocking (ISERDES)

If Regional Clocking is selected as the clocking option, the delay chain feature of the ISERDES is used to delay the inputs (RDat, RCtl) with respect to RDClk. In this case, it is important to determine the optimal delay (IOBDELAY) value for the ISERDES.

The delay chain in the ISERDES is used to delay its inputs (RDat,RCtl) by small increments and enables the sampled data to be shifted relative to the internal RDClk. For statically aligned systems, the delay chain length (set by IOBDELAY in UCF) is a critical part of the system, as is the requirement that the PCB is designed with precise delay and impedance matching for all the differential pair of the LVDS data bus.

Xilinx does not recommend a singular IOBDELAY value that is effective across all hardware platforms. Xilinx also does not recommend attempting to determine the IOBDELAY setting empirically. In addition to the clock-to-data phase relationship, other factors such as package flight time (package skew) and clock routing delays (internal to the device) affect the clock data relationship at the sample point (in the ISERDES) and are difficult to characterize.

Xilinx recommends extensive investigation of the IOBDELAY value setting during hardware integration and debugging. The IOBDELAY value provided with the SPI-4.2 Core in the constraint file (*.ucf) is only a place holder:

INST "<snk_instance_name>/U0/io0/chan*/U1" IOBDELAY_VALUE = 18 ;

This constraint is needed to align the incoming data (RDat and RCtl) to its clock (RDClk) when regional clocking is used. Static alignment is accomplished by delaying the RDat and RCtl inputs in the ISEREDES using the "IOBDELAY_VALUE" attribute. The ISERDES contains a 64-tap delay element with a fixed, guaranteed tap resolution (see the Virtex-4 Data Sheet). The IOBDELAY_VALUE attribute specifies the number of tap delays to use. The possible values are any integer from 0 to 63. The optimal value for IOBDELAY should be determined by careful benchmarking on your hardware system.

AR# 20022
Date 12/15/2012
Status Active
Type General Article