The SPI-4.2 core provides general purpose clocks (*_GP) to the user interface.
* RDClk180_GP is an inverted version of RDClk0_GP (the full rate receive data clock output).
* SysClk180_GP is an inverted version of SysClk0_GP (the full rate clock generated from SysClk).
* For the Source Slave clocking core, SysClk180_GBSLV is an inverted input clock that is phase-shifted 180 degrees from SysClk0_GBSLV.
The SPI-4.2 Core v7.0 is optimized for all Virtex-4 devices. The global clocks and I/O clocks are fully differential in Virtex-4 devices; consequently, the inverted clocks ( RDClk180_GP, SysClk180_GP and SysClk180_GBSLV ) are no longer needed and no longer used in the core. However, they are listed in the instantiation template files (veo/vho).
These unused ports also cause the following NGDBuild warnings:
"WARNING:NgdBuild:454 - logical net 'SysClk180_bufg' has no load."
"WARNING:NgdBuild:454 - logical net '*_pl4_snk_top0/rdclk180_gp' has no load."
To avoid the above warnings, do not use (connect) the following inverted clocks: