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AR# 20034

LogiCORE XAUI v5.0 core - RTL simulation of the "transceiver.v" file in the XAUI core fails because defparams are of type integer instead of type string.

Description

General Description: 

When doing a RTL simulation of the "transceiver.v" instantiation in the XAUI v5.0 core, the simulation fails because the CHAN_BOND_ONE_SHOT and RX_LOSS_OF_SYNC_FSM defparams are incorrectly of type integer.

Solution

In the "transceiver.v" Verilog MGT instantiation, the following code exists: 

 

// synthesis translate_off 

defparam mgt.REF_CLK_V_SEL = 1; 

defparam mgt.CHAN_BOND_MODE = CHBONDMODE; 

defparam mgt.CHAN_BOND_ONE_SHOT = 0; 

defparam mgt.RX_LOSS_OF_SYNC_FSM = 0; 

// synthesis translate_on 

 

The problem is that the CHAN_BOND_ONE_SHOT and RX_LOSS_OF_SYNC_FSM defparam's should be strings instead of integers. Therefore, to workaround this issue, edit this section of the "transceiver.v" file to be: 

 

// synthesis translate_off 

defparam mgt.REF_CLK_V_SEL = 1; 

defparam mgt.CHAN_BOND_MODE = CHBONDMODE; 

defparam mgt.CHAN_BOND_ONE_SHOT = "FALSE"; 

defparam mgt.RX_LOSS_OF_SYNC_FSM = "FALSE"; 

// synthesis translate_on 

 

Note that this issue does not affect implementation, it only affects RTL simulations of the "transceiver.v" instantiation. The VHDL version does not have this problem.

AR# 20034
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article