UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20040

LogiCORE SPI-4.2 (POS-PHY L4) - Timing analyzed (TRCE) reports "0 items analyzed"

Description

General Description 

Timing analyzed (TRCE) reports "0 items analyzed" for the following TIMESPECs:  

 

TS_RDCLK_P  

TS_SysClk_P  

TS_TSClk  

TS_stat_syn_ver_pl4_snk_top0_U0_clk0_RDClk0_dcmo

Solution

This report is expected for the defined TIMESPECs above.  

 

Although these TIMESPECs have 0 paths analyzed, they are used to derive other TIMESPECs that cover the needed paths. Therefore, these TIMESPECs are still needed in the UCF constraint file. 

 

For instance, TIMESPEC TS_pl4_src_clk0_TSClk_dcmo is derived from TIMESPEC TS_TSClk, and it covers the timing constraints for all the TSClk paths.  

 

These timing analyzer messages can be safely ignored.

AR# 20040
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article