We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 20053

Spartan-3/-3E - How do I handle a brown-out condition in Spartan-3/-3E?


How do I handle a brown-out condition in Spartan-3/-3E?


For an FPGA to power up and configure properly on initial power-up, all three supplies (VCCINT, VCCAUX, and VCCO) must exceed the maximum Power-On Reset (POR) voltage in order for the device to proceed with configuration and initialization. The VCCO bank voltage that is monitored on power-up is the bank that powers the configuration pins. This is VCCO_4 for Spartan-3 and VCCO_2 for Spartan-3E.

On subsequent brown-out conditions where the device is not power-cycled (i.e., the supply voltages are not taken down to 0V), either the VCCInt voltage or the VCCAux voltage must be taken down below the minimum POR voltage in order to clear out the device configuration content. Subsequently, both voltages must exceed the maximum POR voltage once again in order for the device to be programmed with the new configuration. Lowering VCCO alone will not trigger a POR because the POR circuitry does not monitor VCCO_4 after initial power-on.

Another method for clearing the configuration contents after a brown-out condition is to drive PROG_B Low.

A brown-out condition is defined by either the VCCINT or VCCAUX rail dropping below its respective data retention voltage defined by VDRINT and VDRAUX in the data sheet.

Please refer to the Spartan-3/-3E Data Sheet for the minimum and maximum POR voltages and data retention voltages.

The Spartan-3 DC and Switching Characteristic Data Sheet is located at:


The Spartan-3E DC and Switching Characteristic Data Sheet is located at:


AR# 20053
Date 12/15/2012
Status Active
Type General Article