How do I determine whether the DONE pin is being held Low externally or if the FPGA has not released the signal?
By default, the DONE pin is an open-drain driver that must be pulled up to achieve a logic High to allow multiple FPGAs to be configured in a serial daisy chain.
When devices are configured in a serial daisy chain, upstream devices are fully programmed before they pass configuration data to downstream devices. After the upstream device is programmed, it releases its DONE pin and waits in the startup sequence until all other FPGAs release their DONE pins and the DONE signal goes High.
Spartan-3 devices contain a programmable internal pull-up resistor on the DONE pad, which is enabled with the DonePin option in BitGen. The default setting is pull-up. The pull-none setting disables the pull-up and should only be used if you are planning to connect an external pull-up resistor to this pin.
Additionally, the DriveDone option in BitGen causes the FPGA to actively drive the DONE signal High instead of simply releasing it. In a serial daisy chain, only the last device can utilize this option (otherwise, an upstream device will actively drive the DONE signal High once its configuration information is loaded, causing contention on the shared DONE signal).
Determining if a Spartan-3 Device has Released its DONE Pin
You can directly determine if the DONE pin has been released by performing an Instruction Capture through JTAG. The Instruction Capture register provides access to the internal "release_done" signal, which releases the DONE pin.
Instruction Capture through JTAG
To perform an Instruction Capture through JTAG, reset the TAP controller and then move to the Shift-IR state. Clock TCK six times while holding TMS=0. The device will clock out the IR Capture value on its TDO pin. Bit 5 of the Instruction_Capture pattern indicates whether the DONE signal has been released. The following is from the Spartan-3 BSDL file:
attribute INSTRUCTION_CAPTURE of XC3S400_FG456 : entity is
-- Bit 5 is 1 when DONE is released (part of startup sequence)
-- Bit 4 is 1 if house-cleaning is complete
-- Bit 3 is ISC_Enabled
-- Bit 2 is ISC_Done
NOTE: The first bit of the IR-Capture register is shifted out when entering the Shift-IR state. The IR-Capture register is shifted out LSB first so 10XXXX is shifted out on TDO.
Double-check the startup sequence options selected for bitstream generation. At the cycle selected for the DONE release, the sequencer always waits in that state until the DONE is externally released. This action is similar to the SyncToDONE behavior in the XC4000 FPGAs. However, this does not hold off the GTS, GSR, or GWE if they are selected to be released prior to DONE. Consequently, DONE is selected first in the sequence for default settings. For a true SyncToDONE behavior, set the GTS, GSR, and GWE cycles to a value of DONE in the BitGen options to cause these signals to transition as DONE externally transitions High.
If the FPGA is daisy-chained, the DONE pin is probably being held Low by one of the other FPGAs. The recommended startup options for Spartan-3 devices are the following: