I am using a DLLIOB (the IOBs adjacent to the GCLK pads) to route a clock to the DLL, and I notice that the DLL never acquires lock even though the input clock meets the CLKIN frequency and jitter specifications. To debug this problem, I routed the clock through the DLLIOB to an output pin. I probed the output pin and found that the clock was not toggling internally even though it was toggling at the input pin. What is causing this problem?
If the DLLIOB is the only IOB in the bank that requires a VREF, then you might potentially run into this problem. This problem occurs because the VREF path to the DLLIOB is not configured correctly due to a bug in BitGen. Consequently, the reference voltage (VREF) at the buffer is close to zero volts instead of the VREF voltage. As a result, the input buffer cannot trigger a logic Low properly, and the output of the input buffer will always be a static High. In some versions of silicon, the reference voltage at the DLLIOB input buffer can be around 0.3-0.4 V even though the VREF path is not configured correctly, which is enough to trigger a logic level Low and allows the input buffer to work correctly.
This problem has been fixed in the latest 6.3i Service Pack available at:
The first service pack containing the fix is 6.3i Service Pack 2.
This problem does not occur if you are using multiple I/Os in the banks that require VREF. If using software prior to 6.3.02i, you can work around this issue by configuring another input in that bank to use an I/O standard that uses VREF. If multiple I/Os that require VREF are used in the same bank, then the bitstream is correctly generated.
For more information on which I/O standards use VREF for Virtex-E, see the Virtex-E Detailed Functional Description data sheet located at:
For more information on which I/O standards use VREF for Spartan-IIE, see the Spartan-IIE Detailed Functional Description data sheet located at: