UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20097

6.3i Virtex-II Pro - "INTERNAL_ERROR:Pack:pktbaplacepacker.c:144:1.23.4.2 - Could not pack comps for ..."

Description

Keywords: -timing

Urgency: Standard

General Description:
In some cases, timing-driven packing incorrectly packs two flip-flops together without regard for whether they have compatible clock signals. This error results in the following internal error:

NOTE: This Answer is only applicable to your design if the error message you encounter contains the "the clock signals don't agree" phrase.

"INTERNAL_ERROR:Pack:pktbaplacepacker.c:144:1.23.4.2 - Could not pack comps for
site SLICE_X40Y32 - The clock signals don't agree.
State: REASON
SkipExpand: True
CompType: SLICE
Reason: 879973056
Frag: fn_egress/TRDE/a_demap/din_odu_i_m2_i_m2[29] (PK_LUT) (89108)
Frag: fn_egress/TRDE/a_demap/un6_dtmp_b_d.G_406 (PK_LUT) (88726)
Frag: fn_egress/TRDE/a_clkm/DOUTG[30] (PK_FLOP) (84896)
Frag:
fn_egress/gmodem_odu2_desynchronizer/f_generator/bch_decoder/decoded_data1[4]
(PK_FLOP) (143870)"

Solution

This problem will be fixed in version 7.1i, scheduled for early 2005. Meanwhile, you can avoid the problem by disabling the failing algorithm by setting the following environment variable:

Windows PC
set PL_NO_GRP_CLUSTER=1

Linux and Solaris Workstations
setenv PL_NO_GRP_CLUSTER 1
AR# 20097
Date Created 10/05/2004
Last Updated 09/26/2006
Status Archive
Type General Article