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AR# 20098

Virtex-4 XtremeDSP Slice - Pipelined rounding for A x B opmode is not supported in some ES devices


The XtremeDSP Slice (DSP48 is the primitive name) supports five modes of rounding that are described in the XtremeDSP Design Considerations User Guide in the "Symmetric Rounding Supported by Carry Logic" section at: 


CarryInSel[1:0] is set to "11" when performing an embedded symmetric round in a multiplication operation. The embedded function performs a XNOR function on the MSB bits of A and B inputs. Consequently, this function is detecting whether the multiplication yields a positive or negative result. This is important because the number 4.5 is positive and subject to a rounding up, and the number -4.5 is negative and subject to a rounding down.  


This functionality is not working for the LX25 and LX60 ES silicon and is not supported. 


The DSP48 element supports five different modes of symmetric rounding. All four non-pipelined rounding modes are fully supported. Only the pipelined Round(A x B) mode (that is, when CarryInSel[1:0] = 11) is not supported.


To work around this problem, implement the required rounding logic in the fabric. For this multiply operation, the XNOR function should be implemented in the fabric. An example section of VHDL code follows: 


cin <= A(17) XNOR B(17); 


Pipeline compensation is also required so that the delay to the CIN port matches the delay through the multiplier. This will be a delay of one, which will require a single register. This register is free in that it is in the same slice as the LUT used to implement the XNOR function. The required second delay is provided by pipelining the CIN input. 


This will not cause a problem in simulation. The problem only exsists in hardware, when the above listed ES devices are used.

AR# 20098
Date 05/16/2014
Status Archive
Type General Article