Keyword: component, ISERDES
NOTE: This issue affects only LX25 ES devices. Production devices have normal functionality of the IDELAY, as described in the Virtex-4 User Guide:
The clock "C" input of the IDELAY element is inverted. Consequently, the control signals in the IDELAY component are synchronous to the falling edge of the clock connected to "C" input. This imposes a specific timing requirement when a design uses the IDELAY element and setting IOBDELAY_TYPE to VARIABLE. Also, the same IDELAY element is used by ISERDES.
Consequently, a design using ISERDES with IOBDELAY_TYPE=VARIABLE and DLYRST, DLYINC, and DLYCE must observe the same timing requirement.
Since the clock polarity is inverted from the rest of the design, the synchronous path for the control signals RST, INC, CE (IDELAY) or DLYRST, DLYINC, DLYCE(ISERDES) must meet one-half the clock cycle. This will ensure proper clock domain transfer for the control signals to the IDELAY element. That is, assuming the source register of the control signals is clocked by the same clock connected to "C" input, the path between the source register to the IDELAY element must meet one-half the clock cycle.
Similarly, when using the ISERDES with DLYRST, DLYINC, and DLYCE signals, these signals must meet one-half the clock cycle of CLKDV.