UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - Adaptable. Intelligent.
  2. Support
  3. AR# 20127: 6.3i Timing Analyzer/TRACE - "WARNING:Timing:2751 - The clock refclk_buf has a period... is an invalid warning"

AR# 20127

6.3i Timing Analyzer/TRACE - "WARNING:Timing:2751 - The clock refclk_buf has a period... is an invalid warning"

Description

Urgency: Hot

General Description:

When I run my 10G Fibre Channel design that uses RocketIO, the timing tools report a false warning:

"WARNING:Timing:2751 - The clock refclk_buf has a period (frequency) specification of 6275 ps (159.36 Mhz). This violates the minimum period (maximum frequency) for component mgt_0_MGT of 6400 ps (156.25 Mhz)."

When is this going to be fixed?

Solution

This problem has been fixed in the latest 6.3i Service Pack available at:

http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 6.3i Service Pack 2.

AR# 20127
Date 01/18/2010
Status Archive
Type General Article
Page Bookmarked