AR# 20182

v2.1 COREGen Aurora - VHDL Pro-X Modules do not initialize

Description

General Description:

VHDL Pro-X modules do not initialize. VHDL does not allow operations to be carried out on port mappings (for example, concatenations of port mapped signals). As a result, signals must be added to the source code when translating Verilog top-level modules to VHDL. The signals that connect the MGT RX interface to the Aurora Lane logic fall under this category: the signals that go to the MGT are a bit selected subset that was handled as a concatenation in the Verilog code. Unfortunately, the LHS is incorrect for the assignment: essentially the signals are connected so that the output signals are double assigned.

Solution

To resolve this in a module generated using COREGen, perform the following steps:

If you have a 2-byte single lane design:

1. Find the following assignments in the code. There will be one set for every lane in the design:

rx_data_#_vec <= open_rx_data_i(48#+47 downto 48#) & rx_data_i(16*#+15 downto 16#);

rxnotintable_#_vec <= open_rx_not_in_table_i(6#+5 downto 6#) & rx_not_in_table_i(2#+1 downto 2#);

rxdisperr_#_vec <= open_rx_disp_err_i(6#+5 downto 6#) & rx_disp_err_i(2#+1 downto 2#);

rxcharisk_#_vec <= open_rx_char_is_k_i(6#+5 downto 6#) & rx_char_is_k_i(2#+1 downto 2#);

rxchariscomma_#_vec <= open_rx_char_is_comma_i(6#+5 downto 6#) & rx_char_is_comma_i(2#+1 downto 2#);

where # is the lane number, starting at 0. So, for example, lane 0 will have a section with:

rx_data_0_vec <= open_rx_data_i(47 downto 0) & rx_data_i(15 downto 0);

rxnotintable_0_vec <= open_rx_not_in_table_i(5 downto 0) & rx_not_in_table_i(1 downto 0);

rxdisperr_0_vec <= open_rx_disp_err_i(5 downto 0) & rx_disp_err_i(1 downto 0);

rxcharisk_0_vec <= open_rx_char_is_k_i(5 downto 0) & rx_char_is_k_i(1 downto 0);

rxchariscomma_0_vec <= open_rx_char_is_comma_i(5 downto 0) & rx_char_is_comma_i(1 downto 0);

2. Switch the LHS and the RHS of the assignment while preserving the widths:

rx_data_i(16*#+15 downto 16#) <= rx_data_#_vec(15 downto 0);

rx_not_in_table_i(2#+1 downto 2#) <= rxnotintable_#_vec(1 downto 0);

rx_disp_err_i(2#+1 downto 2#) <= rxdisperr_#_vec(1 downto 0);

rx_char_is_k_i(2#+1 downto 2#) <= rxcharisk_#_vec(1 downto 0);

rx_char_is_comma_i(2#+1 downto 2#) <= rxchariscomma_#_vec(1 downto 0);

where # is the lane number, starting at 0. So, for lane 2 (for example), you would write:

rx_data_i(47 downto 32) <= rx_data_2_vec(15 downto 0);

rx_not_in_table_i(5 downto 4) <= rxnotintable_2_vec(1 downto 0);

rx_disp_err_i(5 downto 4) <= rxdisperr_2_vec(1 downto 0);

rx_char_is_k_i(5 downto 4) <= rxcharisk_2_vec(1 downto 0);

rx_char_is_comma_i(5 downto 4) <= rxchariscomma_2_vec(1 downto 0);

If you have a 4-byte lane design, the steps are the same, but the names are slightly different:

1. Find the following assignments in the code. There will be one set for every lane in the design:

rx_data_map_i(64*#+63 downto 64#) <= open_rx_data_i(32*#+31 downto 32#) & rx_data_i(32*#+31 downto 32#);

rx_not_in_table_map_i(8*#+7 downto 8#) <= open_rx_not_in_table_i(4*#+3 downto 4#) & rx_not_in_table_i(4*#+3 downto 4#);

rx_disp_err_map_i(8*#+7 downto 8#) <= open_rx_disp_err_i(4*#+3 downto 4#) & rx_disp_err_i(4*#+3 downto 4#);

rx_char_is_k_map_i(8*#+7 downto 8#) <= open_rx_char_is_k_i(4*#+3 downto 4#) & rx_char_is_k_i(4*#+3 downto 4#);

rx_char_is_comma_map_i(8*#+7 downto 8#) <= open_rx_char_is_comma_i(4*#+3 downto 4#) & rx_char_is_comma_i(4*#+3 downto 4#);

where # is the lane number, starting at 0. So, for example, lane 0 will have a section with:

rx_data_map_i(63 downto 0) <= open_rx_data_i(31 downto 0) & rx_data_i(31 downto 0);

rx_not_in_table_map_i(7 downto 0) <= open_rx_not_in_table_i(3 downto 0) & rx_not_in_table_i(3 downto 0);

rx_disp_err_map_i(7 downto 0) <= open_rx_disp_err_i(3 downto 0) & rx_disp_err_i(3 downto 0);

rx_char_is_k_map_i(7 downto 0) <= open_rx_char_is_k_i(3 downto 0) & rx_char_is_k_i(3 downto 0);

rx_char_is_comma_map_i(7 downto 0) <= open_rx_char_is_comma_i(3 downto 0) & rx_char_is_comma_i(3 downto 0);

2. Switch the LHS and the RHS of the assignment while preserving the widths:

rx_data_i(32*#+31 downto 32#) <= rx_data_map_i(64*#+31 downto 64#);

rx_not_in_table_i(4*#+3 downto 4#) <= rx_not_in_table_map_i(8*#+3 downto 8#);

rx_disp_err_i(4*#+3 downto 4#) <= rx_disp_err_map_i(8*#+3 downto 8#);

rx_char_is_k_i(4*#+3 downto 4#) <= rx_char_is_k_map_i(8*#+3 downto 8#);

rx_char_is_comma_i(4*#+3 downto 4#) <= rx_char_is_comma_map_i(8*#+3 downto 8#);

where # is the lane number, starting at 0. So, for lane 2 (for example), you would write:

rx_data_i(95 downto 64) <= rx_data_map_i(159 downto 128);

rx_not_in_table_i(11 downto 8) <= rx_not_in_table_map_i(19 downto 16);

rx_disp_err_i(11 downto 8) <= rx_disp_err_map_i(19 downto 16);

rx_char_is_k_i(11 downto 8) <= rx_char_is_k_map_i(19 downto 16);

rx_char_is_comma_i(11 downto 8) <= rx_char_is_comma_map_i(19 downto 16);

AR# 20182
Date 12/15/2012
Status Archive
Type General Article