AR# 20198

7.1 System Generator for DSP - Why are my clock (CLK)/clock enable (CE) ports missing when I import my VHDL as a black box into System Generator for DSP if I do not use lower case letters?

Description

Why are my clock (CLK)/clock enable (CE) ports missing when I import my VHDL as a black box into System Generator for DSP if I do not use lower case letters?

Solution


This problem occurs because the current parser is case sensitive. Since VHDL is not case sensitive, you simply need to change the (CLK)/clock enable (CE) ports on the entity to all lower case as shown in the following example:



clk : in std_logic;

ce : in std_logic;
AR# 20198
Date 08/09/2011
Status Archive
Type General Article