AR# 20200

6.3 System Generator for DSP - Why is there a behavioral mismatch when simulating the Dual Port BlockRAM?

Description

Keywords: SysGen, MATLAB, Simulink, 6.3, Verilog, dual, port, RAM, BRAM

Urgency: Standard

General Description:
In 6.3 System Generator for DSP, why is there a behavioral mismatch when simulating the Dual Port BlockRAM?

Solution

The problem is that the System Generator for DSP model does not match the Verilog behavioral model. When the reset_b is set, then the output should go to zero, or when the reset_b is Low, the output should return the value of the data_b input. That is what the Verilog behavioral model does.

The problem is that the System Generator for DSP model's output of the B port does not change until we_b goes Low.

This will occur with the No Read On write mode and when the user has selected DPRAM (Dual Port BlockRAM) block with Valid Out ports.
AR# 20200
Date 10/20/2004
Status Archive
Type General Article