How do I use the FIFO block with type "Embedded FIFO" (FIFO16)?
When using the Virtex-4 FIFO16s in System Generator for DSP 6.3 (e.g., FIFO block with memory type set to "Embedded FIFO"), the FIFO MUST have a reset port and that reset MUST be asserted before using the FIFO. Otherwise, the FIFO is not guaranteed to operate properly in hardware.
The FIFO16 documentation states that the reset line must be asserted for three clock cycles continuously to perform a proper reset. The HDL that is generated when embedded FIFO is selected in the System Generator for DSP FIFO block ensures that this constraint is met through the use of a one-hot encoded state machine.
For more information on the FIFO block, see the Xilinx System Generator User Guide, accessible from: