UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20202

EDK 6.2 SP1, Virtex-4 - OPB/PLB DDR controller requires additional timing constraints

Description

General Description: 

In the OPB/PLB DDR SDRAM controllers, the I/O configuration on DQS signals (v1.10.a & v1.11.a) has changed on Virtex-4 devices. Now we will require UCF constraints to constrain the skew on the outputs.

Solution

This change is temporary and will be fixed in the next release of the DDR controller. 

 

The signals affected are the input DQS lines.  

 

An example of the necessary UCF file changes is below. It will vary based on the instance names in the MHS file. 

 

 #Begin UCF snippet 

 

 # Specify DDR_DQS Tsu since register is not in IOB 

 # DDR_DQS PAD to REG delay = 3.0 ns 

 

NET "ddr_dqs<0>" TNM = "DQS_PADS_GRP"; 

NET "ddr_dqs<1>" TNM = "DQS_PADS_GRP"; 

INST "opb_ddr_0/opb_ddr_0/DDR_CTRL_I/IO_REG_I/RDDQS_REG0" TNM = "RDDQS_REGS_GRP"; 

INST "opb_ddr_0/opb_ddr_0/DDR_CTRL_I/IO_REG_I/RDDQS_REG1" TNM = "RDDQS_REGS_GRP"; 

TIMESPEC "TS_DQS_PAD2FFS" = FROM "DQS_PADS_GRP" TO "RDDQS_REGS_GRP" 3.0 ns;  

 

 #End UCF snippet  

 

This problem affects the following cores:  

 

OLB DDR 1.10.a 

PLB DDR 1.11.a 

PLB DDR 1.10.a

AR# 20202
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article