AR# 2022

SYNPLIFY - How do I instantiate and initialize Virtex Select BlockRAM+?

Description

General Description:

How do I instantiate and initialize Virtex Select BlockRAM+ using Synplicity's Synplify?

You can instantiate the RAMB* cells by using the Xilinx family library supplied with Synplify. Please see (Xilinx Solution 244) for details of instantiating Xilinx-specific cells.

NOTE: Tested with Synplify 5.1.4

Solution

Verilog

`include "<synplicity_install>/lib/xilinx/unisim.v"

module block_ram_ex (CLK, WE, ADDR, DIN, DOUT);

input CLK, WE;

input [8:0] ADDR;

input [7:0] DIN;

output [7:0] DOUT;

// synthesis translate_off

defparam

U0.INIT_00 = 256'h0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF,

U0.INIT_01 = 256'hFEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210;

// synthesis translate_on

RAMB4_S8 U0 (.WE(WE), .EN(1'b1), .RST(1'b0), .CLK(CLK),

.ADDR(ADDR), .DI(DIN), .DO(DOUT)) /* synthesis

xc_props="INIT_00=0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF,

INIT_01=FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" */;

endmodule

VHDL

library IEEE;

use IEEE.std_logic_1164.all;

library unisim;

use unisim.vcomponents.all;

library synplify;

use synplify.attributes.all;

entity RAMB4_S8_synp is

generic (INIT_00, INIT_01 : string :=

"0000000000000000000000000000000000000000000000000000000000000000");

port (WE, EN, RST, CLK : in std_logic;

ADDR : in std_logic_vector(8 downto 0);

DI : in std_logic_vector(7 downto 0);

DO : out std_logic_vector(7 downto 0));

end RAMB4_S8_synp;

architecture XILINX of RAMB4_S8_synp is

component RAMB4_S8

port (WE, EN, RST, CLK: in STD_LOGIC;

ADDR: in STD_LOGIC_VECTOR(8 downto 0);

DI: in STD_LOGIC_VECTOR(7 downto 0);

DO: out STD_LOGIC_VECTOR(7 downto 0));

end component;

attribute xc_props of u1 : label is "INIT_00=" & INIT_00 & ",INIT_01=" & INIT_01;

begin

U1 : RAMB4_S8

port map (WE => WE, EN => EN, RST => RST, CLK => CLK,

ADDR => ADDR, DI => DI, DO => DO);

end XILINX;

library IEEE;

use IEEE.std_logic_1164.all;

entity block_ram_ex is

port (CLK, WE : in std_logic;

ADDR : in std_logic_vector(8 downto 0);

DIN : in std_logic_vector(7 downto 0);

DOUT : out std_logic_vector(7 downto 0));

end block_ram_ex;

architecture XILINX of block_ram_ex is

component RAMB4_S8_synp

generic( INIT_00, INIT_01 : string :=

"0000000000000000000000000000000000000000000000000000000000000000");

port (WE, EN, RST, CLK: in STD_LOGIC;

ADDR: in STD_LOGIC_VECTOR(8 downto 0);

DI: in STD_LOGIC_VECTOR(7 downto 0);

DO: out STD_LOGIC_VECTOR(7 downto 0));

end component;

begin

U1 : RAMB4_S8_synp

generic map (

INIT_00 => "0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF",

INIT_01 => "FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210")

port map (WE => WE, EN => '1', RST => '0', CLK => CLK, ADDR => ADDR, DI => DIN,

DO => DOUT);

end XILINX;

AR# 2022
Date 12/15/2012
Status Active
Type General Article