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AR# 20240

LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v5.0 Core - Incorrect alignment when "MGT CRC Enabled" is used results in incorrect IDLE generation


General Description:

The Virtex-II Pro MGT's require that the transmitted /K28.5/ is left-justified in the MGT's internal two-byte data path to ensure that the CRC logic correctly generates IDLE's. For more information, refer to the RocketIO Transceiver User Guide at:


Go to Digital Design Considerations -> CRC (Cyclic Redundancy Check) -> Ports and Attributes -> CRC Format -> Ethernet

However, a problem exists in the Ethernet 1000BASE-X PCS/PMA or SGMII v5.0 Core in which this alignment is not correct. This is only an issue if the "MGT CRC Enabled" option is set to true in COREGen. Otherwise, the CRC logic should be created in FPGA fabric. For example, the CRC logic is implemented inside the Gigabit Ethernet MAC and Tri-Mode Ethernet MAC cores and this is not an issue.


A patch is available that fixes this issue with the RocketIO transceiver wrappers (transceiver.vhd and transceiver.v). Specifically, to ensure correct alignment (left justification) of the /K28.5/ character in the RocketIO internal data path, an extra layer of registers have been added between the Core netlist and the RocketIO transceiver instantiated from the example design. This delays the following RocketIO signals by an extra TXUSRCLK2 period to force the correct alignment of the packet delimiters:


To obtain this fix, please install the patch that is available in the LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v5.0 Core Release Notes and Known Issues Answer Record (Xilinx Answer 19880).

AR# 20240
Date 12/15/2012
Status Active
Type General Article