Description

General Description: 

Why do I get the following error message when I try to generate the LFSR Virtex-4? 

"--------------------------------------- 

From SysGen: 

Error during generation: Error using ==> sim 

Error reported by S-function 'xllfsr' in dsp48_test/LFSR; 

A hardware implementation of this block could not be generated." 

My design cannot be synthesized, and it does not map to a core because the LFSR is not available for the Virtex-4 device.

Solution

Use one of the following methods to work around this issue: 

- Generate the LFSR for Spartan-3 in COREGen and bring that into System Generator for DSP as a blackbox. 

- Create your own LFSR using the System Generator for DSP BlockSet. 

If you are targeting the DUC (Digital Up Converter) v1.2 in System Generator for DSP, you will find that the DDS in Dithering mode uses the LFSR. You can work around the problem by changing the DDS to a different SFDR (Spurious Free Dynamic Range): 

SFDR 60 dB = Truncation 

SFDR 84 dB = Dithering 

SFDR 115 dB = Taylor Series