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AR# 20243

10.1 Timing Analyzer - Why do I get a negative number for minimum clock-to-out time when I run Timing Analyzer with -s min?


For a Virtex-II Pro device, when I run trce -s min to get the minimum clock-to-out time, the result is a negative number. For a synchronous chip-to-chip interface, a negative clock-to-out means that the downstream device must have a negative hold time requirement. Most components have a 0 ns hold time at best and according to the timing reports, interfacing Virtex-II Pro to another device with best-case conditions, it is impossible to produce a negative clock-to-out time.


The Tdcmino delay is too large for the -min speed case; it should cancel the clock delay, resulting in only a data delay for the clock-to-out. It appears to be almost as large as the -7 Tdcmino. This issue is scheduled to be fixed in the next major release of the design tools.

To work around this issue, run a timing simulation with the temperature and voltage of the board. Then, use 40% of these results or use 40% of the worst-case timing analysis results for minimum clock-to-out timings.

The theory behind the negative clock-to-out time is that since the device will never run that fast, you do not need to be concerned with a negative clock-to-out time. If the FPGA has excess negative clock-to-out time, it might be caused by a setup check for the wrong clock edge. Depending on the design, the data would change only once per cycle on the output of the flip-flop, so the data might be valid before the clock edge but it should still be valid until the same point before the next clock edge. Also, the Tdcmino value is off for the minimum speed grade so the device will zero out the clock tree and the result will be the clock-to-out time of the individual flip-flop in the IOB or slice.

AR# 20243
Date 12/15/2012
Status Active
Type General Article