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AR# 20249

7.1i CORE Generator/NetGen - IP Core outputs in post PAR simulation are always X


General Description: 

IP Core outputs in post PAR simulation are always X. Examining the HDL simulation code shows a disconnect at the output bus pins of the core. 




entity NETLIST is  

port (  

M_63_Q : in STD_LOGIC := 'X';  

M_62_Q : in STD_LOGIC := 'X';  

M_30_Q : in STD_LOGIC := 'X';  

M_27_Q : in STD_LOGIC := 'X';  

M_24_Q : in STD_LOGIC := 'X';  

M_7_Q : in STD_LOGIC := 'X';  


M_26_Q : in STD_LOGIC := 'X';  

M_23_Q : in STD_LOGIC := 'X'  




This will happen if the IP core was created with a bit-blasted bus format. Due to a number of possible inaccuracies, the back-annotated simulation netlister (NetGen) is no longer combining bit-blasted busses into standard logic vectors for simulation. This change forces the bus values to X.  


If possible, the IP core should be regenerated using an "in tact" bus format such as B<n:m>. 


Support for the generation of IP Implementation netlists containing bus port names split into "individual bus bits" ("bit-blasted format") is still available in the 8.1i CORE Generator Project options release, but this support is deprecated and will not be available in the next major release of ISE. Please note that there are a number of cores currently in ISE 8.1i which do not support individual bus bit format for the Implementation Netlist. These include the Binary Counter, FIFO Generator, and all Ethernet cores. 


If you wish to use bit-blasted format , you will need to set up the XIL_NLW_BIT_TO_BUS environment variable to 1 in order for the design to process through NetGen as single bus bits. 


If you wish to generate and/or use a CORE Generator IP core with bit-blasted bus format, and would like NetGen to reconstruct the bits as a bus in the HDL simulation netlist, you need to run NetGen with XIL_NLW_BIT_TO_BUS environment variable set to 1.

AR# 20249
Date 11/14/2013
Status Archive
Type General Article
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