We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 20268

8.1i CPLD TSIM Timing Simulation - Post-fit simulation model changes bidirectional (inout) pin to output only


A design that contains a bidirectional I/O at the top level is converted to an output only pin after implementation. This might be seen in the report file as well as the post-fit simulation model.


Bidirectional converted to output in report file as well as timing simulation netlist  


The issue is that the output is always enabled, and the fitter interprets this to mean it is always an output. The input is using an internal feedback path because it is faster than going through the input buffer, so this pin actually is configured to be output only.  


To work around this issue, add an input pin to the design and use it as an output enable on the pin in question. By doing this, the CPLD implementation tools cannot use the internal feedback path and must use the input buffer connected to the pin.  


Bidirectional converted to output in timing simulation netlist only 


This is a bug in the timing netlist writer. There is a problem with the interpretation of the CoolRunner-II open drain signals.  


To work around this issue, use the following additional CPLD fitter command line option "-noopendrain." This prevents the CPLD implementation tools from using one type of open drain configuration in favor of another (logically equivalent), and the resulting timing simulation netlist will correctly show this signal as a bidirectional pin. 


This problem was corrected in 7.1i.

AR# 20268
Date 05/08/2014
Status Archive
Type General Article