We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20272

LogiCORE FIFO Generator v2.0 - GUI allows invalid output depths. The minimum depth must be 16.


General Description: 

When using the FIFO Generator core with the independent clocks (asynchronous clocks), the user is given the option to specify an "Output Data Width" which differs from the "Input Data Width" by a ratio of between 8:1 and 1:8. This is presented to the user as a drop-down selection of seven possible "Output Data Widths". The "Output Depth", then, is calculated from the resulting ratio. 


The core has a restriction that the minimum depth of the port must be 16. However, the GUI selection falsely allows you to select the "output width" which might result in the "output depth" as small as 2. 


For example: 

* Select an "Input Data Width" of 64. 

* Select an "Input Depth" of 32. 

* GUI provides the option of 8,16,32,64,128,256,512 for "Output Data Width". 

* If the user selects an "Output Data Width" from the list of 256 or 512, "Output Depth" is set to 8 or 4, respectively... both of which are <16 and therefore invalid for the core.


When using the core with different input and output width (asymmetric ports), please select the output width carefully, so that the "output depth" is greater than 16. 


The calculated "output depth" will show up in the GUI, as soon as you select the "output width". 


For the shallow input depths less than 32 words, the programmable empty and full thresholds range (upper and lower boundaries ) may overlap. As a result of this, the ranges are invalid. Please manually enter the valid thresholds based on the output depth of the FIFO.

AR# 20272
Date 05/16/2014
Status Archive
Type General Article
Page Bookmarked