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AR# 20278

LogiCORE FIFO Generator - PROG_EMPTY and PROG_FULL can produce false-assertions

Description

In a Built-In FIFO-based FIFO Generator implementation, when the Output Depth is larger than the selected Primitive Depth, it is possible for PROG_EMPTY and PROG_FULL to produce false-assert values if the Programmable Empty or Programmable Full thresholds are near the limits of their range.

Example (PROG_EMPTY):

Input/Output Depth = 4096

Primitive Depth = 1024

Programmable Empty Threshold = 1013

Reading and writing to the FIFO simultaneously, PROG_EMPTY might be asserted for a period of time, even though the number of words in the FIFO is much larger than 1013. (Our test scenario had PROG_EMPTY asserting at 2059 words in this example.)

Cause (PROG_EMPTY):

There are inherent delays when chaining FIFO16 primitives together in depth. Because of the nature of these delays, a read operation can empty the last FIFO slightly before it is refilled by the next FIFO in the chain. In the example above, the 1024-deep primitive was able to empty sufficiently to drop slightly below the 1013-word threshold, at which time the PROG_EMPTY flag is asserted. So, while there might be a total of 2059 words in the FIFO, the PROG_EMPTY warns the user that the number of words in the last FIFO16 has dropped below 1013 words.

Cause (PROG_FULL):

There are inherent delays when chaining FIFO16 primitives together in depth. It is possible for the first FIFO in the chain to fill up before the words from it are able to propagate down the chain and be read from the read interface. As a result, the first FIFO16 could approach FULL much more quickly than the entire design, so PROG_FULL might assert at odd times. The FIFO could report PROG_FULL even when there is nowhere near the specified number of words in the FIFO. This is particularly true for Programmable Full Thresholds near the lower bound of their valid range.

Solution

When using Built-in FIFO configuration, please be sure to enter the correct frequency for the read and write clocks.

The relative frequency of these two clocks are important for generating the FIFO.

AR# 20278
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article