When LVTTL I/O standard is used for SPI4.2 FIFO Status signals (RSClk, RStat(1:0), TSClk, TStat(1:0)), PAR might fail to place all the I/Os in the correct banks during implementation. You might receive an error from PAR such as:
"ERROR:Place - The following 4 components are required to be placed in a specific
relative placement form. The required relative coordinates in the RPM grid
(that can be seen in the FPGA-editor) are shown in brackets next to the
component names. Due to placement constraints it is impossible to place the
components in the required form. IOB SysClk_P (0, 0)
Constrained by statement: COMP "SysClk_P" LOCATE = SITE "BANK4"
LEVEL 1; BUFIO
pl4_implv4_clocking28757_9_pl4_src_top_master_trans0/U0/clk0/sysbio (-1, -4)
(-1, 0) IOB SysClk_N (0, -1)
Constrained by statement: COMP "SysClk_N" LOCATE = SITE "BANK4"
ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in your design
cannot be automatically placed. "
This Answer Record applies only to Virtex-4 and Virtex-5. Virtex-6 does not support LVTTL.
When the LVTTL I/O standard is used for SPI4.2 FIFO Status signals (RSClk, RStat(1:0), TSClk, TStat(1:0)), it is necessary to assign pin-outs for all the I/Os in the design according to the Banking Rules (see Virtex-4 or Virtex-5 FPGA handbook). This is critical to avoid PAR placement errors.
The OIF specification defines the Transmit/Receive Data Path signals' (TDat, TCtl, TDClk, RDat, RCtl, RDClk) I/O standard to be LVDS I/O. These SPI-4.2 Data Path signals should be placed according to the guidelines described in Constraining the Core section of the SPI-4.2 User Guide.
For the SPI-4.2 FIFO Status signals (RSClk, RStat(1:0), TSClk, TStat(1:0)), the I/O standards can be either LVTTL or LVDS I/Os. If LVTTL Standard is used, a VCCO = 3.3V is required, and the appropriate Bank Rules must be obeyed to combine different input and output standards in the same bank.
It is also necessary that all the I/Os in the design, including the user or back-end I/Os, be placed according to the device banking rules.
07/06/2006 - Initial Release
06/24/2009 - Updated with Virtex-6 information