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AR# 20281

LogiCORE SPI-4.2 (POS-PHY L4) v7.1 - SPI-4.2 Simulation with calendar values from COE file are not used


When post-NGDBuild simulation of the Sink and Source netlists is run, the initial contents of the calendar specified in the COE file are not used. 


The post-NGDBuild simulation files were generated using gen_sim_models script.


Solution 1:  


In the SPI-4.2 release, the Sink and Source calendar can be initialized during CORE Generator system operation. When the calendars are initialized, CORE Generator system converts the calendar sequence (specified in the COE file) into implementation constraints, and places these constraints in the UCF file (refer to the SPI-4.2 User Guide, Calendar COE File Format, for more information). During implementation, the UCF calendar constraints are used to initialize the Sink and Source calendar block RAM with the desired sequence.  


By adding UCF calendar constraints to the UCF file, the block RAM of the Sink and Source cores will now contain the correct calendar sequence. However, the gate-level simulation files for the Sink and Source cores have to be manually updated to reflect this programming. The gate level simulation files for the Sink and Source cores are generated by the gen_sim_models script and are available in the following directory:  




To change the simulation models to match the physical implementation, the following steps must be performed. Note that the following steps apply only to a Sink or Source gate-level simulation model delivered in the SPI-4.2 release (i.e., <component_name>_pl4_snk_top.vhd or <component_name>_pl4_src_top.vhd or similar files. If the entire loopback design is run through NGDBuild, or the entire user design is run through NGDBuild, and then NetGen is run, then this gate-level netlist will already contain the correctly initialized calendar sequence, and no further steps are required.)  


1. Generate or modify the top-level UCF files that contain the Sink and Source calendar initialization values. An example of a 4-channel Sink core configuration is shown below for the SPI-4.2 Core (note that unused entries can either be initialized to 0, or left unused, which will also default the values to 0):  


INST ?<component_name>_pl4_snk_top0/U0/cal0/CalRAM/BlockRam?  

INIT_00 = 0000000000000000000000000000000000000000000000000000000003020100;  


2. Copy the UCF calendar constraints into a temporary UCF file called the same name as the SPI-4.2 Core ngc file. For example, if the generated sink netlist is ch4_pl4_snk_top.ngc, then a new UCF should be created with the name ch4_pl4_snk_top.ucf. The calendar initialization portion of the pl4_wrapper.ucf should then be copied into this new UCF file, and the top-level instance name (<component_name>_pl4_snk_top0/ for the Sink Core, <component_name>_pl4_src_top0/ for the Source Core) needs to be removed. For the example above, ?ch4_pl4_snk_top0/" would be removed so that the file appears as:  


INST ?U0/cal0/CalRAM/BlockRam?  

INIT_00 = 0000000000000000000000000000000000000000000000000000000003020100;  


3. Verify that the SPI-4.2 Core netlist and corresponding new UCF files are in the same directory, and then run NGDBuild:  

> ngdbuild ch4_pl4_snk_top  


4. Generate the gate-level simulation netlist. This is accomplished by running NetGen as follows: 

> netgen -sim -ofmt vhdl -xon false ch4_pl4_snk_top.ngd  


5. The resulting gate-level simulation netlist will contain the initialized calendar load logic. Replace the gate-level netlists (created by the gen_sim_models script) that are located in the "<proj>/<component_name>/test/vhdl" directory with the output from NetGen.

AR# 20281
Date 05/16/2014
Status Archive
Type General Article
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