When I am simulating the SPI-4.2 Dynamic Alignment Sink Core, the PhaseAlignComplete signal never asserts and SnkOof remains High, although the start-up sequence in (Xilinx Answer 16176) has been followed. This behavior can be seen in both post-NGDBuild and post-PAR (with SDF) simulations.
With Virtex-4 using Dynamic Phase Alignment, a significant number of cycles is required to complete the initial phase alignment at the startup.
In a device, this only takes a second; however, in a simulation this can take several hours, as you will need to run simulation long enough to see the PhaseAlignComplete assert and SnkOof de-assert. Once the core is in frame, there is no need to perform re-alignment; therefore, this will not affect the overall bandwidth or the performance of the core.
The length of simulation time needed for Dynamic Phase Alignment to complete the alignment will depend on the frequency of RDClk. The following observation has been made:
at RDClk = 400 MHz, PhaseAlignComplete asserted Approximately at 1.8 ms
at RDClk = 311 MHz, PhaseAlignComplete asserted Approximately at 2.2 ms
This may take several hours of simulation run time. To work around this issue, perform one of the following to reduce the simulation time:
Run your simulation in batch mode rather than active GUI mode. For ModelSim simulator, the length of simulation time can be reduced significantly (approximately by half) if simulation is run in a batch mode. Refer to your simulator documentation on how to run simulation in a batch mode, and how to properly save the simulation wave file for viewing at another time.
If you are performing Verilog simulation, Xilinx recommends that you generate a generic VCD file. To generate the VCD file, add the following code to your testbench (pl4_demo_testbench.v):
You should have a "dcm_dv.vcd" file generated in your simulation directory, and be able to load it in the waveform viewer of your simulator.
Another option is to use Static Alignment netlist for functional simulation purposes. Although, the phase alignment process is quite different from Static and Dynamic Phase Alignment, the functionality of the core is identical; therefore, Static Alignment netlist can be used.
Follow the steps below to substitute the dynamic simulation netlist with the static simulation netlist.
1. Open CORE Generator and load the project used to generate the original dynamic phase alignment core.
2. Select the original dynamic phase alignment core that you generated.
3. Using the tool bar, choose to recustomize the core you selected (this will bring up the SPI-4.2 core GUI).
4. Change the "Component Name" option in the GUI to something else.
5. Change the "Configuration" option in the GUI from "Dynamic Alignment" to "Static Alignment."
6. Select the "Generate" button to generate the new core.
7. Once the core is generated, go the "<proj>/<component_name>/test/vhdl" directory, and run the "gen_sim_model" script. This will generate gate level simulation files for the sink and source core. For Verilog, go to the verilog sub-directory instead of VHDL. A "pl4_snk_top.v(vhd)" and "pl4_src_top*.v(vhd)" file will be generated in this current directory.
8. To use the generated static alignment gate level files for simulation, replace the dynamic phase alignment file that you originally used with the newly generated "pl4_snk_top.v(.vhd)" file.
9. Open the newly generated simulation file with a text editor and change the module (or entity name) defined at the top of the file to match the original module (or entity name) you have used for your dynamic phase alignment core.