When I run simulation with the FIFO Generator Core, setup, hold, and recover timing violations occur that are similar to the following:
# ** Warning: */X_FF RECOVERY Low VIOLATION ON SET WITH RESPECT TO CLK; # Expected := 0.556 ns; Observed := 0.036 ns; At : 473.85 ns # Time: 473850 ps Iteration: 0 Instance: /control_tb/u1/u6_notri_asreg # ** Warning: */X_FF RECOVERY Low VIOLATION ON SET WITH RESPECT TO CLK; # Expected := 0.556 ns; Observed := 0.036 ns; At : 473.85 ns # Time: 473850 ps Iteration: 0 Instance: /control_tb/u1/u6_notri_asreg # ** Warning: */X_FF RECOVERY Low VIOLATION ON RST WITH RESPECT TO CLK; # Expected := 0.556 ns; Observed := 0.508 ns; At : 473.862 ns # Time: 473862 ps Iteration: 0 Instance: /control_tb/u1/u3_asreg # ** Warning : */X_FF SETUP Low violation on I with respect to CLK; Expected := 1ns; Observed := 0ns; At : 28306ns Instance /u2_u1_u1_n1541_ffx_sync_ff/u3_asreg
NOTE: The actual message might be different, depending upon the simulator being used.
Source of the Problem
One cause of timing violations might be that the FIFO has different speeds for RD_CLK and WR_CLK. Although different frequencies are allowed, the FIFO has internal signals that cross two clock domains; this means that a synchronization circuit depends on both RD_CLK and WR_CLK. The synchronization circuit is needed for the asynchronous nature of the FIFO. The FIFO will still function properly, regardless of timing violations. If the violation is indeed coming from the flip-flops crossing the two clock boundaries, this violation can be ignored.
Another cause of timing violations is due to the wr_rst and rd_rst flip-flops in the FIFO Generator. The asynchronous RST of the FIFO Generator is synchronized with each respective clock. Depending on the timing of the release of the RST user input, it is possible that there might not be adequate setup time before the clock edge, and the synchronization flops might produce a setup-time violation. This logic has been designed to properly recover from this condition, but the SimPrim X_FF primitive might produce an error or warning during the simulation. The timing violations due to the assertion or de-assertion of reset can be ignored.
For FIFO Generator v4.1 core, the signals related to the crossing of the two clock boundaries contain "_asreg" in the path name. Consequently, they can be ignored. The signals with "_asreg_di" are synchronized; consequently, they are not subject to timing violations.