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AR# 20353

6.3 XPS - How do I bring out particular ports in a processor sub-module to the top-level interface? For example, how do I access Port B of a BRAM at the top-level if port A is connected to the OPB?

Description

Keywords: EDK, MHS, submodule, toplevel, export

Urgency: Standard

General Description:
I want to use the Embedded Development Kit to create a processor system to use as a sub-module in my FPGA system. In this case, the processor system is not the top-level of my design. How do I bring out particular ports of the sub-module to the top-level interface?

Solution

You can solve this issue with a bit of editing in your MHS file. You must add the signals that you want to assign to your top-level to the correct location in your MHS file. The signals must first be assigned to the internal signal under their component instantiation in the MHS file. The signals must be assigned to a top-level port at the top of the MHS file and the signal direction must be stated.

The signals that you want to export to your top-level are listed in the MPD file for the applicable components for the signals. For example, if you want to route a signal (BRAM_WEN_A) from the BRAM connected to your DSOCM bus as an output on your top-level, follow these steps:

1. Copy the signal from the BRAM MPD file (i.e. bram_block_v1_00_a) and paste into the relevant location in your MHS file (i.e. into the bram_block associated with the DSOCM in your MHS file i.e. bram_block) as follows:

BEGIN bram_block
PARAMETER INSTANCE = dsocm_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = dsocm_porta
END

2. Assign this signal to a particular signal name in the bram_block associated with the DSOCM bus as follows:

BEGIN bram_block
PARAMETER INSTANCE = dsocm_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = dsocm_porta
PORT BRAM_WEN_A = sig_a.
END

3. Assign the sig_a signal to an external pin at the top of your MHS file before any component instantiations and state its particular direction as follows:

PORT sig_1 = sig_a, DIR = output.
(where sig_1 is a top_level signal)

PARAMETER VERSION = 2.1.0

PORT ......
PORT........
PORT sig_1 = sig_a, DIR = output.

BEGIN........

These steps will route the particular signal to a top-level pin.
AR# 20353
Date Created 11/10/2004
Last Updated 04/30/2007
Status Archive
Type General Article