UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20370

7.1i ISE Simulator (ISim) - Known Issues with ISE Simulator

Description

Keywords: simulation, problems

Urgency: Standard

General Description:
This Answer Record covers all of the Known Issues for ISE Simulator 7.1i.

Solution

Q1. When running a design for 60 seconds or more of simulation time, ISE seems to freeze up and hang. Why does this occur?
A1. This is a problem with the way the waveforms are currently stored. This problem will be addressed in the ISE 8.1i release of ISE Simulator.

Q2. When I use the Shift key to make multiple selections of signals, then click anywhere in the selected block, it does not add all the signals to the viewer.
A2. This is a known issue with the way the signal selection works. For now, when making multiple selections, you will have to click the last item in the selected block to move the whole block into the viewer. This problem is currently being investigated for a fix in ISE 8.1i.

Q3. I cannot view parameters or generics in the hierarchy view. Is there any way to access this information from the simulator?
A3. ISE Simulator does not currently have the ability to display parameter and generics. The simulator does read the information, but it cannot display it to you. This problem will be addressed in the ISE 8.1i release.

Q4. I am not able to attach a testbench waveform with a package file. It does not create the "tbw" file, and the process dies.
A4. You are not supposed to be able to attach a testbench waveform to a package. This is a problem in ISE, where it allows you to select a package to generate a testbench waveform. This problem will be fixed in ISE 8.1i.

Q5. After installing an ISE Service Pack, the design does not simulate correctly.
A5. After every Service Pack install, it is a requirement to clean up project files before running through the design. To clean up project files, select Project -> Cleanup Project Files from the Project Navigator toolbar.

Q6. When I type "help" and "HELP," I receive different results in the ISE Simulator console window.
A6. This is a known issue with TCL in the Windows Operating System environment. The TCL interface in the simulation console supports simulation commands as well as all valid System Environment commands, such as HELP. Therefore, "HELP" will access the Windows System help command, and "help" will access the ISE Simulator help. There is no fix scheduled for this issue.

Q7. ISE Simulator is not optimized to be a structural simulator, and this is why some structural netlists (Post-translate/post-MAP/post-PAR) can cause the simulator to hit its maximum limits during compilation.
A7. One way to fix this is to maintain hierarchy in the netlist. For more information, refer to the Synthesis and Verification Guide:
http://toolbox.xilinx.com/docsan/xilinx7/books/docs/sim/sim.pdf

Q8. ISE Simulator HDL Editor does not support generics or parameters. If there are any generics or parameters in the top-level file, they will not be used in the testbench waveform.
A8. This feature will be supported in the 8.1i release of ISE Simulator HDL Editor.

Q9. When stepping through the code in the console window, the focus changes from the console window to the HDL Editor window as a new file is opened.
A9. This is currently a limitation of the ISE Simulator. To work around this issue, either use the step button (see ISE Simulator help for details), or click back to the main console window as needed. This issue will be addressed in ISE 8.1i.

Q10. When stepping through the code in the console window, it encounters a non-existent file and displays multiple messages stating that the file does not exist.
A10. To work around this issue, run the simulation beyond the point of the non-existent file. This issue will be addressed in ISE 8.1i.

Q11. When using Generate Expected Results in a design that contains only bi-directional ports, this does not do anything.
A11. The Generate Expected Simulation does not work when using bi-directional signals. This will be fixed in ISE 9.1i.

Q12. ISE Simulator errors out when the ISE design tools are installed in a directory containing spaces.
A12. ISE Simulator will not work if the Xilinx installation is in a directory with spaces. This issue will be fixed in ISE 8.1i.

Q13. Changing the generated HDL language from Verilog to VHDL or vice-versa does not work for schematic designs.
A13. See (Xilinx Answer 20995).

Q14. When setting the end of testbench to a large number, such as 500,000 ns, ISE seems to freeze up and hang. Why does this occur?
A14. This is a problem with the way the waveforms are currently stored. There is a memory leak issue here. This problem will be addressed in the 8.1i release of ISE Simulator.

Q15. ISE Simulator does not open the GUI if the user is not an Administrator or a Power User.
A15. See (Xilinx Answer 21126).

Q16. ISE Simulator becomes unstable and produces incorrect results when a restart is performed.
A16. This is a known issue with ISE Simulator. This issue will be fixed in ISE 8.1i.

Q17. Generate Expected Results does not work correctly in ISE Simulator.
A17. The Generate Expected Simulation Results is supposed to write to self-checking testbench for the user and check against these outputs in the simulation. This flow is not working properly. This issue will be fixed in ISE 8.1i

Q18. Typing a step prior to a Run command runs only up to 0 ns and states that initialization is done.
A18. See (Xilinx Answer 21633).

Q19. The VHDL file written out has an extra "." in the VHDL library declaration.
A19. See (Xilinx Answer 21880).

Q20. Test Bench Waveform does not work for bi-directional ports.
A20. See (Xilinx Answer 21900).

Q21. Test Bench Waveform does not work for asynchronous inputs.
A21. When an input signal is set to asynchronous, the input values are not correctly written into the generated testbench. To work around this issue, make the input synchronous to one of the clock inputs. This issue will be fixed in ISE 8.1i.

Q22. Test Bench Waveform pattern wizard adds random numbers to the end of the pattern.
A22. When a specific non-random pattern is used with the waveform creation tool and then the pattern is changed to a non-random pattern, it seems as if the numbers are now random for some of them. This problem is currently being investigated.
AR# 20370
Date Created 09/03/2007
Last Updated 11/13/2007
Status Archive
Type General Article