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AR# 20392

6.3i SimPrim, Timing Simulation - OSERDES writes out "U"s on the output when doing a timing simulation (Virtex-4 / VHDL)


General Description:

When doing a timing simulation with an OSERDES block, only "U"s come out on the output port. Also when the OSERDES is cascaded, the SHIFTOUT writes out "U" as well.


This problem has been fixed in the latest 6.3i Service Pack available at:

The first service pack containing the fix is 6.3i Service Pack 3.
AR# 20392
Date 04/04/2012
Status Archive
Type General Article
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