When running PAR on a design containing ChipScope cores, the following warning might be encountered:
WARNING:Place - The structured logic associated with a shift register could not be placed in such a way as to use the appropriate fast connections. Shift registers should flow through every slice down through the clb(s) that they use. The relative placement required by the logic was impossible to resolve.
The following components are involved in this logic:
This warning can be safely ignored. The tool is just letting you know that it cannot cascade the SRL16Cs in the most optimal way possible. This placement is what is needed for ChipScope to run as it is optimally cascading the carry logic that is connected to the SRL16C's. This warning will be removed in the 7.1 release.