What is the maximum number of Simultaneously Switching Outputs (SSO) allowed? What is the maximum number of I/Os that can drive their maximum current simultaneously at VCCO?
Xilinx does not characterize the CPLD device packages to estimate the maximum number of SSOs before ground bounce. When limited testing was performed on CPLD SSOs, a load of 35 pF indicated that you should not have more than eight simultaneously switching outputs on the entire chip (i.e., all banks). If loading is less than 35 pF, you should be able to have more outputs switching simultaneously.
If you do need to have more than eight SSOs, Xilinx recommends that you consider altering the slew rate setting on these outputs to skew the outputs relative to each other. By following this recommendation, you can avoid ground bounce due to SSOs and your design will function correctly.
Also, the CPLD data sheets do not indicate how many I/Os can drive a steady current (8 mA for instance) simultaneously. For more information, see (Xilinx Answer 1308).