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AR# 20422

6.3 Speed File/Timing - What has changed in the Virtex-4 version 1.50 of the Speed File?

Description

Keywords: version, 1.50, speed, file

Urgency: Standard

General Description:
What has changed in version 1.50 of the Virtex-4 Speed File?

Solution

Timing values associated with the FIFO16 and the PCI Core changed in the Speed File.

For OSERDES, when 3-state ports are used in BUF mode, the setup/hold checks are not checked with respect to T1 and CLK anymore. Since 3-state ports are in BUF mode, we fixed the T1 -> CLK timing checks.

The Relative Min Factors will no longer be applied to the IDELAY component delays. The default delay for the IDELAY component was increased to produce a negative or zero hold time.

The Relative Min Factor has also increased by 15% for the appropriate components and delays.

The master and slave sides of differential inputs are fixed to match each other.
AR# 20422
Date Created 11/29/2004
Last Updated 03/27/2007
Status Archive
Type General Article