UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20424

EDK 6.3, opb_timer_v1_00_b - Reset signal does not reset TINT bits

Description

General Description: 

For the opb_timer_v1_00_b, when OPB_Rst is asserted then released, all bits of the TCSR registers should be reset to '0'. All bits follow this rule with the exception of the TINT bits. With the TINTn bit set to '1', a reset on OPB_Rst does not affect the state of this bit.

Solution

The only way to put this bit to '0' is to perform a write of '1' to the bit, which then changes the state to '0'. Writing a '1' to the bit is a normal mode of operation, but asserting the OPB_Rst should also clear this TINTn bit. The TINTn bit is correctly reset to zero upon power up. 

 

To work around the problem, write a '1' to the bit.

AR# 20424
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article