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AR# 20464

LogiCORE PCI-X - Why does the PCI-X Core tranmit 64-bit initiator request of less than 3 quadwords as a 32-bit request?


General Description:

Under the "Basic Initiator Control" section of the PCI-X User Guide on page 77, it states:

"64-bit wide data transfer is requested by setting bit 28. If used with a memory command or a split completion, and the requested transfer is at least three QWORDS, setting this bit will result in a 64-bit data transfer request on the bus. Otherwise, the transfer will take place as a 32-bit data transfer."

Why is this?


This eliminates some undesirable corner cases related to the deassertion of FRAME#.

Yes, if you have one QWORD, it is possible to do a single 64-bit transfer. But it raises some corner cases that would have to be addressed.

For example, if you assert FRAME# and REQ64#, for your single dataphase QWORD transfer, and then deassert those signals immediately to indicate you are doing one dataphase. What if the target responds only with DEVSEL# and not ACK64#? Then, only one DWORD transfers, and then you have to finish the transfer because you indicated it was one dataphase. So you have to start a second transfer to move the other DWORD.

In developing the core, it was decided that small transfers should be transformed as 32-bit only, so that situations such as this do not happen. The trade off is:

* always have a "couple" more dataphases for small transfers

(constant, small overhead ~50%)


* sometimes have to do multiple transfers

(system dependent, large overhead >100%)

If you only have 32 bits of data, you should do a 32-bit transfer.

AR# 20464
Date 12/15/2012
Status Active
Type General Article
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