We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20472

6.3i SP3 UniSim, SimPrim Simulation - Locked Signal goes Low when doing a variable phase shift in the DCM and DCM_ADV models


Keywords: UniSim, simulation, ModelSim, NC-Verilog DCM, lock, VCS, Verilog, low, variable, phase, DCM, Virtex-4, Virtex-II, Virtex-IIPro, Virtex-II Pro

When doing a variable phase shift with the DCM and the DCM_ADV models, the LOCK signal goes Low a couple of times.


This is a problem in the simulation model for the DCM and the DCM_ADV components. The problem will be seen in both behavioral and timing simulation.

This issue is fixed in ISE 7.1i.

If an immediate fix is required, please open a web case at http://www.xilinx.com/support.
AR# 20472
Date 10/16/2008
Status Archive
Type General Article
Page Bookmarked