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AR# 20511

9.1i Virtex-4 PAR - Placer errors due to the routing limitations of BUFRs in Virtex-4


My design fails during placement, and I have noticed that all of the components that are failing to place are clocked by a BUFR clock buffer. 


Why is this happening? 


Phase 6.9 

"WARNING:Place:119 - Unable to find location. MULT component 

UwbPhyRx_wba/GfDoutQ_upper_2_3[12:0] not placed. 

DSP48 "UwbPhyRx_wba/GfDoutQ_upper_2_3[12:0]". 


WARNING:Place:119 - Unable to find location. SLICEL component 

UwbPhyRx_wba/loop8.peakdetected133_cry_1/O not placed. 

SLICEL "UwbPhyRx_wba/loop8.peakdetected133_cry_1/O"


BUFR clock buffers are able to drive loads in up to only three clock regions, the region containing the BUFR and the adjacent regions above and below. BUFRs in the top and bottom regions will be limited to two regions. Examination of the design in question reveals that the BUFR is driving many more components than would fit in three clock regions. This was the reason that the placer failed to find a location for many of the components. A BUFG should be used instead, if available.

AR# 20511
Date 05/16/2014
Status Archive
Type General Article
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