The XC3S1500 FPGA Errata describes an issue where certain VREF pins on the fg676 package are labeled as VREF pins, but these pins are not actually VREF pins on the 3s1500 silicon.
The software mis-programs these pins when using an I/O standard that requires VREF (voltage reference) inputs such as GTL, SSTL, and HSTL.
Because of this mis-programming, the effective VREF voltage will be lower than expected.
The errata specifies that the work-around is to implement the design and then use FPGA Editor to edit the settings for the I/O sites D25 and F25.
The work-around is to configure both pins as a three-state output buffer and force the buffer into the high-impedance state by driving the T-input high.
How do I do this with using FPGA Editor? Can I automate this process?
This task can be automated by using an FPGA Editor script.
This script can be downloaded from the following link:
The script will modify the NCD file so that pins D25 and F25 will be forced to a high-impedance state.
After running the script, you can verify that the changes were made by viewing the modified NCD file in FPGA Editor and viewing IOB sites D25 and F25.
You will see that the 3-state buffer in the I/Os are enabled and the enable pin is tied to VCC forcing it into a high-impedance state.
Two different methods can be used to run the script.
1) Command line - The script can be run through the command line version of FPGA Editor (fpga_edline), using the following steps:
2. FPGA Editor - The script can be run in FPGA Editor by following these steps:
When generating a bit file for the new NCD file, you will need to turn off the DRC (Design Rule Check) option in BitGen.
If you are creating a bit file through ISE, you can do this by right-clicking Generate Programming File and selecting properties.
Under the general options tab, uncheck the setting to run DRC.
If you are using the command line version of BitGen to generate the bit file, you can disable the DRC setting by inserting the -d option.
bitgen -d <design>.ncd <design>.bit