UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20532

EDK 6.3 - OPB_EMC 1.10.b input/output/3-state registers cannot be packed into IOBs

Description

General Description: 

The registers in the OPB_EMC and the PLB_EMC, pushed outside of the IOBs, which causes reasonable offset-out-after constraints to fail.  

 

The input register resets are qualified in "emc.vhd" by input_datareg_rst. Because this signal is not the same as the 3-state and output register reset signals (Bus2IP_Rst), these registers cannot share the IOB so one of the two is left outside and that makes it fail timing. 

 

The reason that the 3-state registers cannot be pushed into the IOB is because the registers are optimized down to one register and all of the 3-state lines are driven from the one slice register. A save attribute will probably keep XST from doing this optimization.  

 

This has been fixed in emc_common_v2_00_a, which is included in OPB_EMC_V2_00_A.

Solution

This problem is fixed in the latest 6.3 EDK Service Pack, available at: 

http://www.xilinx.com/ise/embedded/edk.htm.
The first service pack containing the fix is EDK 6.3 Service Pack 2.

AR# 20532
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article