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AR# 20574

CPLD CoolRunner-II - What is the minimum/maximum input frequency for the clock divider?

Description

What is the minimum and maximum input frequency for the clock divider?

Solution

The clock divider is not PLL or DLL based, so there is no minimum clock frequency nor is a constant clock source required.

The minimum input of the parameter global clock pulse width, High or Low (TCW), is defined. These minimum inputs are then used to determine a minimum cycle time and frequency.

For example :

XC2C256-7 Tcw = 2.2ns

The maximum clock divider input frequency = 1/(2.2ns + 2.2ns) = 227 MHz

AR# 20574
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article