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AR# 20614

6.3.p03 System Generator for DSP - Release Notes/README


General Description:

This Answer contains the Release Notes for System Generator for DSP 6.3.p03.


Patch Install Instructions

1. Before you install this patch, make sure that you have the following installed on your machine:

- ISE 6.3i Implementation tools and the latest Xilinx Service Pack.

- ISE 6.3i Latest IP Update. You also need to download and install the xFFT v3.1 patch. Please see (Xilinx Answer 20709).

- System Generator for DSP 6.3

- R13, R13.1, or R14 from MathWorks (with the appropriate version of System Generator 6.3. Different versions of MATLAB require different instances of System Generator 6.3)

2. Download the "sysgen6_3_p03.zip" file to a temporary directory, for example to C:\Temp.

3. If you have any MATLAB sessions open, close them and restart MATLAB.

4. In the MATLAB command window, enter the following to start the installation process:

> cd C:\Temp

> xlInstallIP('sysgen6_3_p03.zip');

Follow any prompts from the GUI. The files are installed into your System Generator for DSP 6.3 for installation. The version information is updated to reflect the installation of the patch.

5. Restart MATLAB.

6. To check the version information, enter the following in the MATLAB command window:

> xlVersion

Patch Fixes

In 6.3 System Generator for DSP, why do I receive an error message stating that Verilog is not supported, even when I have VHDL selected in the Xilinx System Generator Block? Please see (Xilinx Answer 20120).

Why do I receive the error "CarryIn Select cannot be set to 1 when not using PCIN, or P" when attempting to use the rounding capabilities of the DSP48? Please see (Xilinx Answer 20338).

Why is FFT v3.1 with Virtex-4 support not available in System Generator for DSP? Please see (Xilinx Answer 20618).

Why does the DSP48 Primitive simulate with an extra cycle of latency when "Consolidate Control Ports" option is selected? Please see (Xilinx Answer 20619).

Why do I see HDL simulation mismatches when the DSP48 PREG is not used? Please see (Xilinx Answer 20620).

I cannot control the DSP48 LEGACY_MODE setting. Please see (Xilinx Answer 20621).

Why is my design larger if I use the DSP48 macro, rather than building the same logic using the DSP48 primitive and muxes? Please see (Xilinx Answer 20622).

How can I reduce the fanout on the clock enable logic to decrease the routing delays? Please see (Xilinx Answer 20623).

Why do I have a simulation mismatch when using the Delay Block retiming option in my Verilog design? Please see (Xilinx Answer 20624).

Why do I receive a stack trace error when the generated address is outside the addressable range of my DPRAM block (dual port block memory block)? Please see (Xilinx Answer 206253).

Why do I receive a port mismatch error when using a hardware in the Loop Co-Simulation block in a configurable subsystem? Please see (Xilinx Answer 20626).

NOTE: Updates to the XtremeDSP Development Kit have also been included in this patch release.

Known Issues

For System Generator for DSP 6.3 Known Issues, please see (Xilinx Answer 20008).

AR# 20614
Date 12/15/2012
Status Active
Type General Article