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  3. AR# 20620: 6.3.p03 System Generator for DSP - Why do I see HDL simulation mismatches when the DSP48 PREG is not used?

AR# 20620

6.3.p03 System Generator for DSP - Why do I see HDL simulation mismatches when the DSP48 PREG is not used?

Description

General Description: 

Why do I see HDL simulation mismatches when the DSP48 PREG is not used?

Solution

This has been fixed in System Generator 6.3.p03. 

 

http://www.xilinx.com/products/software/sysgen/sg_intro.htm

AR# 20620
Date 05/16/2014
Status Archive
Type General Article