General Description:
How can I reduce the fanout on the clock enable logic to decrease the routing delays?
In System Generator 6.3.p03, additional pipeline registers have been added to the output of the clock enable generation logic. These additional registers can be used by synthesis tools to reduce fanout and make it easier to route clock enable signals for high speed designs. For more information, see:
http://www.xilinx.com/products/software/sysgen/sg_intro.htm
| AR# 20623 | |
|---|---|
| Date | 05/19/2014 |
| Status | Archive |
| Type | General Article |