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AR# 20654

9.1i ISE- Automatic VHDL test bench creation creates array bounds (-9999 to -9999)


Keywords: array, sdt_logic_vector, bounds, signal, index, template, left, right, VHDL, vhdl, attribute

When creating a new VHDL testbench using Project->New Source->VHDL testbench, the testbench template that is created incorrectly labels a signal as standard_logic_vector(-9999 to -9999).


The test bench creation tool is not able to handle some port constructs which include VHDL attributes.

For example:
new_sig is array (old_sig'left to old_sig'right)

This is legal syntax and will pass through most synthesis tools (including XST). However, the test bench template will be created with std_logic_vector(-9999 to -9999).

The test bench will need to be manually edited to correct the vector bounds, or replacing the 'left and 'right with constants will allow the template to be created correctly.
AR# 20654
Date 04/16/2009
Status Archive
Type General Article
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