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AR# 20694

Virtex-4 Speed Specs - Global clock line delay is larger than Virtex-II/-II Pro. Is this expected?

Description

Keywords: global, clock, delay, Virtex-II Pro

Urgency: Standard

General Description:
I am comparing the timing report between Virtex-4 and Virtex-II Pro.

Virtex-4 15, Speed grade:11
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

Timing constraint: OFFSET = OUT 5.100 nS AFTER COMP "clk_ibufg" ;

8 items analyzed, 8 timing errors detected.
Minimum allowable offset is 7.036ns.
--------------------------------------------------------------------------------
Slack: -1.936ns (requirement - (clock arrival + clock path + data path + uncertainty))
Source: Mshreg_qg<3>_3 (FF)
Destination: qg<3> (PAD)
Source Clock: clk_ibufg_g rising at 0.000ns
Requirement: 5.100ns
Data Path Delay: 2.959ns (Levels of Logic = 1)
Clock Path Delay: 4.052ns (Levels of Logic = 2)
Clock Uncertainty: 0.025ns
Timing Improvement Wizard
Clock Path: clk_ibufg to Mshreg_qg<3>_3
Location Delay type Delay(ns) Logical Resource(s)
------------------------------------------------- -------------------
B14.I Tiopi 0.648 clk_ibufg
u_global_ibuf
BUFGCTRL_X0Y18.I0 net (fanout=1) 0.495 clk_ibufg_i
BUFGCTRL_X0Y18.O Tbgcko_O 0.265 u_global_bufg
OLOGIC_X0Y65.CLK net (fanout=16) 2.644 clk_ibufg_g
------------------------------------------------- ---------------------------
Total 4.052ns
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

Virtex-II Pro 20, Speed Grade: 6

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Timing constraint: OFFSET = OUT 5.100 nS AFTER COMP "clk_ibufg" ;

8 items analyzed, 0 timing errors detected.
Minimum allowable offset is 4.816ns.
--------------------------------------------------------------------------------
Slack: 0.284ns (requirement - (clock arrival + clock path + data path + uncertainty))
Source: Mshreg_qg<5>_4 (FF)
Destination: qg<5> (PAD)
Source Clock: clk_ibufg_g rising at 0.000ns
Requirement: 5.100ns
Data Path Delay: 2.621ns (Levels of Logic = 0)
Clock Path Delay: 2.195ns (Levels of Logic = 2)
Clock Uncertainty: 0.000ns

Clock Path: clk_ibufg to Mshreg_qg<5>_4
Location Delay type Delay(ns) Logical Resource(s)
------------------------------------------------- -------------------
AB13.I Tiopi 0.866 clk_ibufg
u_global_ibuf
BUFGMUX4P.I0 net (fanout=1) 0.013 clk_ibufg_i
BUFGMUX4P.O Tgi0o 0.056 u_global_bufg
W13.OTCLK1 net (fanout=16) 1.260 clk_ibufg_g
------------------------------------------------- ---------------------------
Total 2.195ns



The global clock line delay in Virtex-4 seems much larger than Virtex-II Pro, and is causing my offset out constraint to fail. Is this expected?

Solution

The timing report above is expected. In Virtex-4, the global line delay is larger. Therefore, the pad-to-pad clock to out (without a DCM) will be longer compared to Virtex-II Pro, and the timing report is reporting this correctly.

NOTE: Please use the latest speed file available.

In Virtex-4, the global lines are designed to reduce skew and duty cycle distortion. However, this results in larger absolute delay (or "latency").

A DCM can be used to reduce the absolute delay. When a DCM is used, the global clock delay will be de-skewed, thus reducing the pad-to-pad (or the clock to out) number.

The following is an example that Virtex-4 reports when using DCM with the same constraint:

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Timing constraint: OFFSET = OUT 5.100 nS AFTER COMP "CLKIN_IN1" ;

8 items analyzed, 0 timing errors detected.
Minimum allowable offset is 3.181ns.
--------------------------------------------------------------------------------
Slack: 1.919ns (requirement - (clock arrival + clock path + data path + uncertainty))
Source: u1_Mshreg_qg<7>_2 (FF)
Destination: qg<7> (PAD)
Source Clock: CLK0_OUT rising at 0.000ns
Requirement: 5.100ns
Data Path Delay: 2.859ns (Levels of Logic = 1)
Clock Path Delay: 0.237ns (Levels of Logic = 3)
Clock Uncertainty: 0.085ns

Clock Path: CLKIN_IN1 to u1_Mshreg_qg<7>_2
Location Delay type Delay(ns) Logical Resource(s)
------------------------------------------------- -------------------
Y6.I Tiopi 0.648 CLKIN_IN1
instance_name_CLKIN_IBUFG_INST
DCM_ADV_X0Y1.CLKIN net (fanout=2) 0.986 CLKIN_IBUFG_OUT_OBUF
DCM_ADV_X0Y1.CLK0 Tdmcko_CLK -5.152 instance_name_DCM_ADV_INST
BUFGCTRL_X0Y1.I0 net (fanout=1) 0.940 instance_name_CLK0_BUF
BUFGCTRL_X0Y1.O Tbgcko_O 0.265 instance_name_CLK0_BUFG_INST
OLOGIC_X1Y29.CLK net (fanout=17) 2.550 CLK0_OUT
------------------------------------------------- ---------------------------
Total 0.237ns
-----------------------------------------------------
COMPARISON:

V2PRO clock path delay without DCM: 2.195ns
V4 clock path delay without DCM: 4.052ns
V4 clock path delay with DCM: 0.237ns
AR# 20694
Date Created 01/26/2005
Last Updated 03/27/2007
Status Archive
Type General Article