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AR# 20711

4.2.03i CORE Generator - CORE Generator cannot generate FIFOs, ROM, or RAM for Spartan/4k/4kxl with ISE Classic install


Keywords: Spartan, Spartanxl, Spartan-XL, xc4000, 4kxl, FIFO, RAM, fifo, ram, distributed, classic, elaborate, internal error

With ISE Classic, when I try to generate a FIFO, ROM or RAM, I receive the following error:

"Preparing to elaborate core...
Elaborating the module...
ERROR: An internal error has occurred. To resolve this error, please consult the Answers Database at http://support.xilinx.com
ERROR: Sim has a problem implementing the selected core. Implementation netlist will not be generated.
ERROR: SimGenerator: Failure of Sim to implement customization parameters core <core_name>
ERROR: Did not generate EDIF implementation netlist (.EDN) file for core <<core_name>>.
Generating the .VHO/.VHD simulation support files...
Generating the .VEO/.V simulation support files...
Generating the .ASY symbol file...
Generating ISE symbol file...
WARNING: Warnings and/or errors encountered while generating <core_name>
(<Core Type>) All output products requested may not have been generated.
ERROR: Elaboration failure for core <Core Type>

WARNING: Not all output products were generated successfully. Please check the console or coregen.log for details.
ERROR: Elaboration of core <Core Type> failed."

Other IP cores can be generated with no problem.


A fix for this problem is available at:

"IP_42_corefix.zip" contains the files needed to allow ISE Classic users the ability to create FIFO, ROM, and RAM cores using the CORE Generator tool. These files were inadvertently left out of the ISE Classic install.

Download "IP_42_corefix.zip" and extract to the "%Xilinx%\coregen\ip\Xilinx\primary\com\Xilinx" directory, where the "%Xilinx%" directory is the install location for ISE Classic 4.2.03i.
AR# 20711
Date 09/02/2008
Status Archive
Type General Article