When the Checkbox to use external RAM is NOT selected the CORE Generator GUI shows the signals "S_ADDR, P_ADDR, WR_D_OUT, and RD_D_IN" as disabled. However, when the core is generated, the instantiation template still has these signals. It seems to have used the correct settings internally because the core uses 47 BRAMs as it should when internal RAM is used.
The core is correctly using internal BRAM, but the instantiation template still has the external RAM port. These ports can be left unconnected.
Please see (Xilinx Answer 30168) for a detailed list of LogiCORE 3GPP2 Turbo Convolutional Code Decoder Release Notes and Known Issues.