When I run a simulation and there are block RAM collisions, the simulation stops after encountering the first collision and does not continue. Why does this occur?
The VHDL LRM does not explicitly define what to do when an ERROR is asserted. In the case of NCSIM, the simulator will exit on an error assertion (this is the default behavior).
You can change the default by adding the following to the NCSIM command line:
set assert_stop_level = failure
An example is shown below:
ncsim -input "@database -open -shm nc; probe -create -database nc -all -memories -depth all; set assert_stop_level failure; run 200ns; quit" tb
If you are not sure how to make this change when running NCSIM, contact Cadence Design Systems.