We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20859

NCSIM, 7.1i - When I run a simulation and there are block RAM collisions, simulation stops and does not continue


General Description: 

When I run a simulation and there are block RAM collisions, the simulation stops after encountering the first collision and does not continue. Why does this occur?


The VHDL LRM does not explicitly define what to do when an ERROR is asserted. In the case of NCSIM, the simulator will exit on an error assertion (this is the default behavior).  


You can change the default by adding the following to the NCSIM command line: 

set assert_stop_level = failure 


An example is shown below: 


ncsim -input "@database -open -shm nc; probe -create -database nc -all -memories -depth all; set assert_stop_level failure; run 200ns; quit" tb 


If you are not sure how to make this change when running NCSIM, contact Cadence Design Systems.

AR# 20859
Date 05/19/2014
Status Archive
Type General Article
Page Bookmarked